sp5055 2.6ghz bidirectional i 2 c bus controlled synthesiser january 2005 the sp5055 is a single chip frequency synthesiser designed for tv tuning systems. control data is entered in the standard i 2 c bus format. the device contains 4 addressable current limited outputs and 4 addressable bi-directional open collector ports one of which is a 3 bit adc. the information on these ports can be read via the i 2 c bus. the device has one fixed i 2 c bus address and 3 programmable addresses, programmed by applying a specific input voltage to one of the current limited outputs. this enables 2 or more synthesisers to be used in a system. features complete 2.6ghz single chip system programmable via i 2 c bus low power consumption (5v 65ma) low radiation phase lock detector varactor drive amp disable 6 controllable outputs, 4 bi-directional 5 level adc variable i 2 c bus address for multi tuner applications full esd protection* * normal esd handling procedures should be observed. applications satellite tv high if cable tuning systems 1 8 charge pump crystal q1 crystal q2 sda scl ? i/o port p7 * i/o port p6 ? i/o port p5 mp16 16 9 drive output v ee rf input rf input v cc p0 output port port p3/add select i/o port p4 ? sp 5055s ? = logic level i/o * = 3-bit adc input fig. 1 pin connections ?top view ordering information sp5055gs/kg/mp as 16 pin soic tubes sp5055gs/kg/mpad 16 pin soic tape & reel sp5055gs/kg/mpcs 16 pin soic* tubes sp5055gs/kg/mpcd 16 pi n soic* tape & reel *pb free matte tin 1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copy rig ht 2 00 1-2005, zarlink semi conduc tor inc. all rig hts res er ve d.
2 sp5055 electrical characteristics t amb = -20 v cc = 5v 500mhz to 2.6ghz sinewave 120mhz, see fig. 5 input voltage = v cc input voltage = 0v when v cc = 0v i sink = 3ma byte 4, bit 2 = 0, pin 1 = 2v byte 4, bit 2 = 1, pin 1 = 2v byte 4, bit 4 = 1, pin 1 = 2v v pin 16 = 07v v out = 12v v out = 132v v out = 0.7v v out = 132v v pin 10 = 13.2v v pin 10 = 0v see table 3 for adc levels w ww ww ww ww jow ww ww ww ww w j w www www wwww wwww www www www www w rowpww rowpww 9urww 9urww w pwww pwww 9oxorwww 9oxorwww 8www 8www dl dpowd9 dpowd9 dpowd9 9owx 9owx 9owx 9owx 9owx 9 d d d d8 l l drowdd drowdd cu8 cu8 dr dr co:o8 co:o8 r r t value conditions r/ 9// g / r// 9/ hr/ /3h 9/ 83h br r/ 8 units 3 3 ? ? ?
3 sp5055 functional description the sp5055 is programmed from an i 2 c bus. data and clock are fed in on the sda and scl lines respectively as defined by the i 2 c bus format. the synthesiser can either accept new data (write mode) or send data (read mode). the tables in fig. 3 illustrate the format of the data. the device can be programmed to respond to several addresses, which enables the use of more than one synthesiser in an i 2 c bus system. table 4 shows how the address is selected by applying a voltage to p3. the last bit of the address byte (r/w) sets the device into read mode if it is high and write mode if it is low. when the sp5055 receives a correct address byte it pulls the sda line low during the acknowledge period and during following acknowledge periods after further data bytes are programmed. when the sp5055 is programmed into the read mode the controlling device accepting the data must pull down the sda line during the following acknowledge period to read another status byte. write mode (frequency synthesis) when the device is in the write mode bytes 2 + 3 select the synthesised frequency while bytes 4 + 5 select the output port states and charge pump information. once the correct address is received and acknowledged, the first bit of the next byte determines whether that byte is interpreted as byte 2 or 4, a logic 0 for frequency information and a logic 1 for charge pump and output port information. additional data bytes can be entered without the need to re-address the device until an i 2 c stop condition is recognised. this allows a smooth frequency sweep for fine tuning or afc purposes. if the transmission of data is stopped mid-byte (i.e., by another device on the bus) then the previously programmed byte is maintained. frequency data from bytes 2 and 3 is stored in a 15-bit shift register and is used to control the division ratio of the 15- bit programmable divider which is preceded by a divide-by- 16 prescaler and amplifier to give excellent sensitivity at the local oscillator input; see fig 5. the input impedance is shown in fig 7. the programmed frequency can be calculated by multiplying the programmed division ratio by 16 times the comparison frequency f comp . when frequency data is entered, the phase comparator, via the charge pump and varactor drive amplifier, adjusts the local oscillator control voltage until the output of the programmable divider is frequency and phase locked to the comparison frequency. the reference frequency may be generated by an external source capacitively coupled into pin 2 or provided by an on- board 4mhz crystal controlled oscillator. note that the comparison frequency is 78125khz when a 4mhz reference is used. bit 2 of byte 4 of the programming data (cp) controls the current in the charge pump circuit, a logic 1 for 6 bit latch port information prescaler 4 16 pre amp 15 bit programmable divider f div f comp divider 4 512 osc 4mhz q1 crystal q2 lock det charge pump control data latch t0 cp power on detector i 2 c bus transceiver os logic gate phase comp f 15 bit latch divider ratio p0 p3 p4 p5 p6 p7 address select 3 bit adc 3 ttl level comp charge pump drive/ varicap out v cc v ee sda scl rf in rf in 15 12 16 1 3 2 13 14 5 4 11 10 9 8 7 6 3g8gg
4 sp5055 a0 0 1 0 1 0 voltage input to p6 0.6v cc to 13.2v 045v cc to 06v cc 03v cc to 045v cc 015v cc to 03v cc 0 to 0.15v cc wpow9wwxw4lodorbwwwwwwfwwro xww9wtwwjwwrwwwwww wdwwwtwwwwwwwwwww wwwwwwww4wdbt wwwwwwwwww wtwww8owrww:w4jlojdojrbwwww wwwxwwjt wxwwjwwwwwwjww wwwwwwwwow wwwwwt jj jwwjwwwwtw9twwjwf wwwwwtw8t wdwwww4wwb byte 1 byte 2 byte 3 byte 4 byte 5 address programmable divider programmable divider charge pump and test bits i/o port control bits 1 2 14 2 6 cp p6 0 2 13 2 5 t1 p5 0 2 12 2 4 t0 p4 0 2 11 2 3 1 p3 ma0 2 9 2 1 1 x ma1 2 10 2 2 1 x a a a a a msb 1 0 2 7 1 p7 lsb 0 2 8 2 0 os p0 wlwwww4wwwb byte 1 byte 2 address status byte 1 fl 0 i2 0 i1 0 i0 ma0 a1 ma1 a2 a a 1 por 1 a0 a : acknowledge bit ma1, ma0 : variable address bits (see table 4) cp : charge pump current select t1 : test mode selection t0 : charge pump disable os : varactor drive output disable switch p7, p6, p5, p4, : control output states p3, p0 por : power on reset indicator fl : phase lock detect flag i2, i1, i0 : digital information from ports p7, p5 and p4, respectively a2, a1, a0 : 5 level adc data from p6 (see table 3) x : don't care w9wjw ma0 0 1 0 1 ma1 0 0 1 1 voltage input to p3 0v to 02v cc always valid 03v cc to 07v cc 08v cc -13.2v a1 0 1 1 0 0 a2 1 0 0 0 0 wpwjw twpww
5 sp5055 9 10 11 12 13 16 16 15 8 7 6 5 4 3 1 2 1n 1n 18p 180n 39n 22k 0.1 4mhz crystal p4 p5 p6 p7 scl sda p3 p0 if signal +5v +12v +30v 22k 2n3904 afc output i 2 c bus varicap input oscillator output v t if section control micro satellite tuner sp 5055s application a typical application is shown in fig. 4. all input/output interface circuits are shown in fig. 6. fig. 5 typical input sensitivity frequency (mhz) operating window 1000 120 500 2000 3000 2600 100 50 150 3000 v in (mv rms into 50 ? ) fig. 4 typical application
6 sp5055 fig. 6 sp5055 input/output interface circuits v ref rf inputs 500 500 v cc 170 charge pump drive output scl / sda rf input loop amplifier ports p7-p4 scl and sda inputs reference oscillator ports p0 and p3 v cc 3k ack * * on sda only v cc crystal q1 crystal q2 port v cc port v cc port p3 only 12k
7 sp5055 port in off state port in on state port in on state with v cc applied v cc not applied all ports off v vp-p v v v ma v v v v v v c c c/w c/w mw 7 2.5 14 6 14 50 v cc +0.3 v cc +0.3 v cc +0.3 v cc +0.3 v cc +0.3 5.5 +125 +150 111 41 440 fig. 7 typical input impedance value parameter absolute maximum ratings all voltages are referred to v ee and pin 3 at 0v min. 12 13, 14 6-11 6-9 10, 11 6-11 13, 14 1 16 2 4, 5 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -55 conditions units max. pin supply voltage rf input voltage port voltage total port output current rf input dc offset charge pump dc offset drive dc offset crystal oscillator dc offset sda, scl input voltage storage temperature junction temperature mp 16 thermal resistance, chip-to-ambient mp 16 thermal resistance, chip-to-case power consumption at 5.5v
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